diff options
| author | Jes Klinke <jbk@google.com> | 2020-10-14 13:24:32 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-19 07:03:37 +0000 |
| commit | 5c80519466863ae7b8579f1edb90829f7f9ee03d (patch) | |
| tree | 27136cf23aa6d1f844b26dbc2a2958cbeebf16f9 /src/soc/intel/skylake/xhci.c | |
| parent | d5faa90df50c820ed3b79d4a5e479767efd73287 (diff) | |
volteer+vendorcode: Retrieve Cr50 version only via SPI
No recent Chromebooks have used I2C for TPM communication, and as a
result, a bug has crept in. The ability to extract Cr50 firmware string
is only supported via SPI, yet code in mainboard and vendorcode attempt
to do so unconditionally.
This CL makes it such that the code also compiles for future designs
using I2C. (Whether we want to enhance the I2C protocol to be able to
provide the version string, and then implement the support is a separate
question.)
This effort is prompted by the desire to use reworked Volteer EVT
devices for validating the new Ti50/Dauntless TPM. Dauntless will
primarily be using I2C in upcoming designs.
BRANCH=volteer
TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x
Change-Id: Ida1d732e486b19bdff6d95062a3ac1a7c4b58b45
Signed-off-by: jbk@chromium.org
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/xhci.c')
0 files changed, 0 insertions, 0 deletions