diff options
| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2016-08-23 14:31:23 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-31 20:02:07 +0200 |
| commit | 1222a73205bd3a0faba988411b4aec6ea8de1059 (patch) | |
| tree | a2257201ba2a5c6b8fe3b3ee1779ac86956d43ed /src/soc/intel/skylake/vr_config.c | |
| parent | 874a8f961ff537bc12cfca3d9937a07fcda2fe6e (diff) | |
skylake: Add initial FSP2.0 support
Add Initial pieces of code to support fsp2.0 in skylake keeping
the fsp1.1 flow intact.
The soc/romstage.h and soc/ramstage.h have a reference to
fsp driver includes, so split these header files for
each version of FSP driver.
Add the below files,
car_stage.S:
Add romstage entry point (car_stage_entry).
This calls into romstage_fsp20.c and aslo handles
the car teardown.
romstage_fsp20.c:
Call fsp_memory_init() and also has the callback
for filling memory init parameters.
Also add monotonic_timer.c to verstage.
With this patchset and relevant change in kunimitsu mainboard,
we are able to boot to romstage.
TEST= Build and Boot Kunimitsu with PLATFORM_USES_FSP1_1
Build and Boot Kunimitsu to romstage with PLATFORM_USES_FSP2_0
Change-Id: I4309c8d4369c84d2bd1b13e8ab7bfeaaec645520
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16267
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/skylake/vr_config.c')
| -rw-r--r-- | src/soc/intel/skylake/vr_config.c | 27 |
1 files changed, 15 insertions, 12 deletions
diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 40223e32cd..17ccd7dd93 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -14,6 +14,8 @@ * */ +#include <fsp/api.h> +#include <soc/ramstage.h> #include <soc/vr_config.h> /* Default values for domain configuration. PSI3 and PSI4 are disabled. */ @@ -80,9 +82,10 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = { }, }; -void fill_vr_domain_config(SILICON_INIT_UPD *params, int domain, - const struct vr_config *chip_cfg) +void fill_vr_domain_config(void *params, + int domain, const struct vr_config *chip_cfg) { + FSP_SIL_UPD *vr_params = (FSP_SIL_UPD *)params; const struct vr_config *cfg; if (domain < 0 || domain >= NUM_VR_DOMAINS) @@ -94,14 +97,14 @@ void fill_vr_domain_config(SILICON_INIT_UPD *params, int domain, else cfg = &default_configs[domain]; - params->VrConfigEnable[domain] = cfg->vr_config_enable; - params->Psi1Threshold[domain] = cfg->psi1threshold; - params->Psi2Threshold[domain] = cfg->psi2threshold; - params->Psi3Threshold[domain] = cfg->psi3threshold; - params->Psi3Enable[domain] = cfg->psi3enable; - params->Psi4Enable[domain] = cfg->psi4enable; - params->ImonSlope[domain] = cfg->imon_slope; - params->ImonOffset[domain] = cfg->imon_offset; - params->IccMax[domain] = cfg->icc_max; - params->VrVoltageLimit[domain] = cfg->voltage_limit; + vr_params->VrConfigEnable[domain] = cfg->vr_config_enable; + vr_params->Psi1Threshold[domain] = cfg->psi1threshold; + vr_params->Psi2Threshold[domain] = cfg->psi2threshold; + vr_params->Psi3Threshold[domain] = cfg->psi3threshold; + vr_params->Psi3Enable[domain] = cfg->psi3enable; + vr_params->Psi4Enable[domain] = cfg->psi4enable; + vr_params->ImonSlope[domain] = cfg->imon_slope; + vr_params->ImonOffset[domain] = cfg->imon_offset; + vr_params->IccMax[domain] = cfg->icc_max; + vr_params->VrVoltageLimit[domain] = cfg->voltage_limit; } |