diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-10-05 19:47:47 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-10-26 15:39:40 +0000 |
| commit | 0f91f79447b63b846fe0da770404bf18833f1306 (patch) | |
| tree | bfce597f2a795a1194803afec57666e17dba3508 /src/soc/intel/skylake/vr_config.c | |
| parent | a9e07f94448650b3a9a27062775c642f8939464b (diff) | |
soc/intel/skylake: drop support for FSP 1.1
This drops support for FSP 1.1 in soc/intel/skylake, after all boards
have been migrated to FSP 2.0, which is backwards compatible.
Any moving of files happens in a follow-up commit to make review easier.
Change-Id: I0dd2eab0edfda0545ff94c3908b8574d5ad830bd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35813
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/vr_config.c')
| -rw-r--r-- | src/soc/intel/skylake/vr_config.c | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index fc23640415..2be9c7175d 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -48,20 +48,6 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = { .icc_max = VR_CFG_AMP(34), .voltage_limit = 1520, }, -#if CONFIG(PLATFORM_USES_FSP1_1) - [VR_RING] = { - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 0, - .psi4enable = 0, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(34), - .voltage_limit = 1520, - }, -#endif [VR_GT_UNSLICED] = { .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), @@ -246,7 +232,6 @@ static uint16_t get_sku_icc_max(int domain) return 0; } -#if CONFIG(PLATFORM_USES_FSP2_0) static uint16_t get_sku_ac_dc_loadline(const int domain) { static uint16_t mch_id = 0, igd_id = 0; @@ -316,7 +301,6 @@ static uint16_t get_sku_ac_dc_loadline(const int domain) } return 0; } -#endif void fill_vr_domain_config(void *params, int domain, const struct vr_config *chip_cfg) @@ -348,7 +332,6 @@ void fill_vr_domain_config(void *params, vr_params->IccMax[domain] = get_sku_icc_max(domain); vr_params->VrVoltageLimit[domain] = cfg->voltage_limit; -#if CONFIG(PLATFORM_USES_FSP2_0) if (cfg->ac_loadline) vr_params->AcLoadline[domain] = cfg->ac_loadline; else @@ -357,5 +340,4 @@ void fill_vr_domain_config(void *params, vr_params->DcLoadline[domain] = cfg->dc_loadline; else vr_params->DcLoadline[domain] = get_sku_ac_dc_loadline(domain); -#endif } |