soc/intel/skylake: Add support for GSPI controller

Sky Lake PCH contains two GSPI controllers. Using the common GSPI
controller driver implementation for Intel PCH, add support for GSPI
controller buses on Sky Lake/Kaby Lake.

BUG=b:35583330

Change-Id: I29b1d4d5a6ee4093f2596065ac375c06f17d33ac
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19099
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 5 insertions, 23 deletions

diff --git a/src/soc/intel/skylake/spi.c b/src/soc/intel/skylake/spi.c
index 4a2ae9d8b8..e11e13f763 100644
--- a/src/soc/intel/skylake/spi.c
+++ b/src/soc/intel/skylake/spi.c
@@ -20,6 +20,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <device/spi.h>
+#include <intelblocks/gspi.h>
 #include <soc/ramstage.h>
 #include <spi-generic.h>
 
@@ -39,31 +40,12 @@ static const struct spi_ctrlr flash_spi_ctrlr = {
 	.setup = flash_spi_ctrlr_setup,
 };
 
-static int gspi_ctrlr_get_config(const struct spi_slave *dev,
-				struct spi_cfg *cfg)
-{
-	if (dev->cs != 0) {
-		printk(BIOS_ERR, "%s: Unsupported device "
-		       "bus=0x%x,cs=0x%x!\n", __func__, dev->bus, dev->cs);
-		return -1;
-	}
-
-	cfg->clk_phase = SPI_CLOCK_PHASE_FIRST;
-	cfg->clk_polarity = SPI_POLARITY_LOW;
-	cfg->cs_polarity = SPI_POLARITY_LOW;
-	cfg->wire_mode = SPI_4_WIRE_MODE;
-	cfg->data_bit_length = 8;
-
-	return 0;
-}
-
-static const struct spi_ctrlr gspi_ctrlr = {
-	.get_config = gspi_ctrlr_get_config,
-};
-
 const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
 	{ .ctrlr = &flash_spi_ctrlr, .bus_start = 0, .bus_end = 0 },
-	{ .ctrlr = &gspi_ctrlr, .bus_start = 1, .bus_end = 2 },
+#if !ENV_SMM
+	{ .ctrlr = &gspi_ctrlr, .bus_start = 1,
+	  .bus_end =  1 + (CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX - 1)},
+#endif
 };
 
 const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);