diff options
| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2015-07-23 17:40:32 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-08-19 14:04:31 +0000 |
| commit | 188e37072fbd79a7a947a903f9918a49f32a08d6 (patch) | |
| tree | b45ef3ce6c30b573be37e297f5bca7d66bfc8548 /src/soc/intel/skylake/smmrelocate.c | |
| parent | 5c1c3d69dd47e11bea2e3f61eeb17ed13e5a8e0d (diff) | |
Skylake: update cbmem_top
cbmem_top was using CHIPSET_RESERVED_MEM_BYTES to w/a unknown memory
regions reserved by fsp for chipset use. With that being removed, the
function needs to properly walk though the memory map resulted from fsp
memory init to find out the usable address for cbmem root.
Refer the FSP 1.3.0 Integartion guide for more details on the Memory
Map.
systemagent should also use the same mechanism to create the reserved
RAM resource.
BRANCH=None
BUG=None
TEST=Build and Boot kunimitsu (FAB3)
CQ-DEPEND=CL:*226035,CL:*226045,CL:291573
Original-Change-Id: Id0954cf8e6388e549c7d4df67b468572b5bea539
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291611
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Robbie Zhang <robbie.zhang@intel.com>
Change-Id: I4e716170f40936081ce9d4878bf74c75f469f78d
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: http://review.coreboot.org/11239
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/smmrelocate.c')
| -rw-r--r-- | src/soc/intel/skylake/smmrelocate.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 2f75c2eebf..4b6f1c4b60 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -54,8 +54,8 @@ static inline void write_uncore_emrr(struct smm_relocation_params *relo_params) "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n", relo_params->uncore_emrr_base.lo, relo_params->uncore_emrr_mask.lo); - wrmsr(UNCORE_EMRR_PHYS_BASE_MSR, relo_params->uncore_emrr_base); - wrmsr(UNCORE_EMRR_PHYS_MASK_MSR, relo_params->uncore_emrr_mask); + wrmsr(UNCORE_PRMRR_PHYS_BASE_MSR, relo_params->uncore_emrr_base); + wrmsr(UNCORE_PRMRR_PHYS_MASK_MSR, relo_params->uncore_emrr_mask); } static void update_save_state(int cpu, |