diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-07-13 23:20:51 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-15 08:32:22 +0200 |
| commit | e0a49147a6e16987bfd267bb76f7cf146ddf03dc (patch) | |
| tree | dc398ce7d03f989f7e7cccd0f696a44514d07c2c /src/soc/intel/skylake/smihandler.c | |
| parent | 1b6196dec95e12ae44b5cfe62073c3dcd3f52686 (diff) | |
soc/intel/skylake: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: I5f2aa424a167092b570fda020cddce5ef906860a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15671
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Diffstat (limited to 'src/soc/intel/skylake/smihandler.c')
| -rw-r--r-- | src/soc/intel/skylake/smihandler.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index c5e6c821c6..1834815611 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -129,34 +129,34 @@ static void southbridge_smi_sleep(void) /* Figure out SLP_TYP */ reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); - slp_typ = (reg32 >> 10) & 7; + slp_typ = acpi_sleep_from_pm1(reg32); /* Do any mainboard sleep handling */ - mainboard_smi_sleep(slp_typ-2); + mainboard_smi_sleep(slp_typ); if (IS_ENABLED(CONFIG_ELOG_GSMI)) /* Log S3, S4, and S5 entry */ - if (slp_typ >= 5) - elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2); + if (slp_typ >= ACPI_S3) + elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); /* Clear pending GPE events */ clear_gpe_status(); /* Next, do the deed. */ switch (slp_typ) { - case SLP_TYP_S0: + case ACPI_S0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break; - case SLP_TYP_S1: + case ACPI_S1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break; - case SLP_TYP_S3: + case ACPI_S3: printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); /* Invalidate the cache before going to S3 */ wbinvd(); break; - case SLP_TYP_S5: + case ACPI_S5: printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); /*TODO: cmos_layout.bin need to verify; cause wrong CMOS setup*/ s5pwr = MAINBOARD_POWER_ON; @@ -190,7 +190,7 @@ static void southbridge_smi_sleep(void) enable_pm1_control(SLP_EN); /* Make sure to stop executing code here for S3/S4/S5 */ - if (slp_typ > 1) + if (slp_typ >= ACPI_S3) hlt(); /* |