diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2016-10-25 19:58:27 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2016-10-27 16:30:54 +0200 |
| commit | 8d01902bb78e25c750f796ea2645d17672f4b9a3 (patch) | |
| tree | 891dd1f1624c91add97e26b32896e648794e2e24 /src/soc/intel/skylake/smihandler.c | |
| parent | f0ba2259b84c1f5083dab14925351ddf8b245e11 (diff) | |
skylake: Add support for eSPI SMI events
Add the necessary infrastructure to support eSPI SMI events,
and a mainboard handler to pass control to the EC.
BUG=chrome-os-partner:58666
TEST=tested on eve board with eSPI enabled, verified that lid
close event from the EC during firmware will result in an SMI
and shut down the system.
Change-Id: I6367e233e070a8fca053a7bdd2534c0578d15d12
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17134
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake/smihandler.c')
| -rw-r--r-- | src/soc/intel/skylake/smihandler.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 1834815611..872cce1e15 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -361,6 +361,12 @@ static void southbridge_smi_gpi(void) gpi_clear_get_smi_status(&smi_sts); } +void __attribute__((weak)) mainboard_smi_espi_handler(void) { } +static void southbridge_smi_espi(void) +{ + mainboard_smi_espi_handler(); +} + static void southbridge_smi_mc(void) { u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN); @@ -482,6 +488,7 @@ static smi_handler_t southbridge_smi[SMI_STS_BITS] = { [PM1_STS_BIT] = southbridge_smi_pm1, [GPE0_STS_BIT] = southbridge_smi_gpe0, [GPIO_STS_BIT] = southbridge_smi_gpi, + [ESPI_SMI_STS_BIT] = southbridge_smi_espi, [MCSMI_STS_BIT] = southbridge_smi_mc, [TCO_STS_BIT] = southbridge_smi_tco, [PERIODIC_STS_BIT] = southbridge_smi_periodic, |