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authorDuncan Laurie <dlaurie@chromium.org>2016-10-25 19:58:27 -0700
committerDuncan Laurie <dlaurie@chromium.org>2016-10-27 16:30:54 +0200
commit8d01902bb78e25c750f796ea2645d17672f4b9a3 (patch)
tree891dd1f1624c91add97e26b32896e648794e2e24 /src/soc/intel/skylake/smi.c
parentf0ba2259b84c1f5083dab14925351ddf8b245e11 (diff)
skylake: Add support for eSPI SMI events
Add the necessary infrastructure to support eSPI SMI events, and a mainboard handler to pass control to the EC. BUG=chrome-os-partner:58666 TEST=tested on eve board with eSPI enabled, verified that lid close event from the EC during firmware will result in an SMI and shut down the system. Change-Id: I6367e233e070a8fca053a7bdd2534c0578d15d12 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17134 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake/smi.c')
-rw-r--r--src/soc/intel/skylake/smi.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/smi.c b/src/soc/intel/skylake/smi.c
index 77f395126a..442607f2e7 100644
--- a/src/soc/intel/skylake/smi.c
+++ b/src/soc/intel/skylake/smi.c
@@ -62,11 +62,12 @@ void southbridge_smm_enable_smi(void)
* - on APMC writes (io 0xb2)
* - on writes to SLP_EN (sleep states)
* - on writes to GBL_RLS (bios commands)
+ * - on eSPI events (does nothing on LPC systems)
* No SMIs:
* - on microcontroller writes (io 0x62/0x66)
* - on TCO events
*/
- enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
+ enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS);
}
void southbridge_trigger_smi(void)