diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-05-12 18:23:27 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-07-16 17:24:48 +0200 |
| commit | 1d14b3e926c15027f9272f1e80b8913fef8cf25d (patch) | |
| tree | b3d89ad4bb1b0ea5ac05d1d7dc6cbf26ec93e6c3 /src/soc/intel/skylake/smbus_common.c | |
| parent | b000513741d330947bb832a5835378e35bdfb394 (diff) | |
soc/intel: Add Skylake SOC support
Add the files to support the Skylake SOC.
Matches chromium tree at 927026db
BRANCH=none
BUG=None
TEST=Build and run on a Skylake platform
Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10341
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/smbus_common.c')
| -rw-r--r-- | src/soc/intel/skylake/smbus_common.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/src/soc/intel/skylake/smbus_common.c b/src/soc/intel/skylake/smbus_common.c index 41416c712c..fea9d805ee 100644 --- a/src/soc/intel/skylake/smbus_common.c +++ b/src/soc/intel/skylake/smbus_common.c @@ -4,6 +4,7 @@ * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com> * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,7 +17,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <arch/io.h> @@ -65,9 +66,9 @@ int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address) unsigned char global_status_register; unsigned char byte; - if (smbus_wait_until_ready(smbus_base) < 0) { + if (smbus_wait_until_ready(smbus_base) < 0) return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - } + /* Setup transaction */ /* Disable interrupts */ outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); @@ -89,9 +90,8 @@ int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address) smbus_base + SMBHSTCTL); /* Poll for transaction completion */ - if (smbus_wait_until_done(smbus_base) < 0) { + if (smbus_wait_until_done(smbus_base) < 0) return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } global_status_register = inb(smbus_base + SMBHSTSTAT); @@ -100,9 +100,8 @@ int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address) /* Read results of transaction */ byte = inb(smbus_base + SMBHSTDAT0); - if (global_status_register != (1 << 1)) { + if (global_status_register != (1 << 1)) return SMBUS_ERROR; - } return byte; } |