soc/intel: Use config_of()

Change-Id: I0727a6b327410197cf32f598d1312737744386b3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Guckian

2 files changed, 8 insertions, 10 deletions

diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 2bbab475af..2d0de2f5e9 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -39,26 +39,26 @@
 /* SOC initialization before RAM is enabled */
 void soc_pre_ram_init(struct romstage_params *params)
 {
+	const struct soc_intel_skylake_config *config;
+
 	/* Program MCHBAR and DMIBAR */
 	systemagent_early_init();
 
-	const struct device *const dev = pcidev_path_on_root(PCH_DEVFN_LPC);
-	const struct soc_intel_skylake_config *const config =
-		dev ? dev->chip_info : NULL;
+	config = config_of_path(PCH_DEVFN_LPC);
+
 	/* Force a full memory train if RMT is enabled */
-	params->disable_saved_data = config && config->Rmt;
+	params->disable_saved_data = config->Rmt;
 }
 
 /* UPD parameters to be initialized before MemoryInit */
 void soc_memory_init_params(struct romstage_params *params,
 			    MEMORY_INIT_UPD *upd)
 {
-	const struct device *dev;
 	const struct soc_intel_skylake_config *config;
 
 	/* Set the parameters for MemoryInit */
-	dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0);
-	config = dev->chip_info;
+
+	config = config_of_path(PCH_DEVFN_LPC);
 
 	/*
 	 * Set IGD stolen size to 64MB.  The FBC hardware for skylake does not
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 6884a324a8..b15fa89292 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -326,13 +326,11 @@ static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg,
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
-	const struct device *dev;
 	const struct soc_intel_skylake_config *config;
 	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
 	FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
 
-	dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0);
-	config = dev->chip_info;
+	config = config_of_path(PCH_DEVFN_LPC);
 
 	soc_memory_init_params(m_cfg, config);
 	soc_peg_init_params(m_cfg, m_t_cfg, config);