diff options
author | Felix Singer <felixsinger@posteo.net> | 2020-07-25 10:03:37 +0200 |
---|---|---|
committer | Michael Niewöhner <c0d3z3r0@review.coreboot.org> | 2020-07-29 20:57:21 +0000 |
commit | 87aecf811dcf56fa326dc644da4c29e453167cce (patch) | |
tree | 8d1b101b443d3f549fc21f83108c337fb55f3744 /src/soc/intel/skylake/romstage | |
parent | ffe90c528b0487ce47a123ae905be8823c5615ae (diff) |
soc/intel/skylake: Enable TraceHub depending on devicetree configuration
Currently TraceHub gets enabled by the option EnableTraceHub, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the TraceHub controller.
I checked all corresponding mainboards if the devicetree
configuration matches the EnableTraceHub setting.
Change-Id: Idcd1e5035bc66c48620e4033d8b4988428e63db9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43847
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/romstage')
-rw-r--r-- | src/soc/intel/skylake/romstage/romstage.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 8e789bce80..76f7a7304c 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -293,7 +293,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) /* DCI and TraceHub configs */ m_t_cfg->PchDciEn = config->PchDciEn; - m_cfg->EnableTraceHub = config->EnableTraceHub; + + dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); + m_cfg->EnableTraceHub = dev ? dev->enabled : 0; m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size; m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size; |