diff options
| author | Usha P <usha.p@intel.com> | 2019-12-23 13:21:36 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-26 10:44:00 +0000 |
| commit | 5395123b849da143d9621b67a6837defe9501acf (patch) | |
| tree | 33850e558e35eb4443aadd46bd22dec062412112 /src/soc/intel/skylake/romstage | |
| parent | f96c638a60fdca149a716e773749c20bd4080ee3 (diff) | |
soc/intel/skylake: Rename pch_init() code
This patch renames pch_init function to bootblock_pch_init and
romstage_pch_init according to the stage it is defined in.
TEST=Able to build and boot soraka successfully.
Change-Id: Idf7b04edc3fce147f7957561ce7d5a0cd05f53fe
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/skylake/romstage')
| -rw-r--r-- | src/soc/intel/skylake/romstage/pch.c | 6 | ||||
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage.c | 2 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/romstage/pch.c b/src/soc/intel/skylake/romstage/pch.c index 88a7cc7163..8e783da6f9 100644 --- a/src/soc/intel/skylake/romstage/pch.c +++ b/src/soc/intel/skylake/romstage/pch.c @@ -17,11 +17,11 @@ #include <intelblocks/tco.h> #include <soc/romstage.h> -void pch_init(void) +void romstage_pch_init(void) { - /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + /* Program TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); - /* Program SMBUS_BASE_ADDRESS and Enable it */ + /* Program SMBUS_BASE_ADDRESS and enable it */ smbus_common_init(); } diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index d381caa104..51428dfe28 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -147,7 +147,7 @@ void mainboard_romstage_entry(void) /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* Program PCH init */ - pch_init(); + romstage_pch_init(); ps = pmc_get_power_state(); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); |