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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-05 15:10:18 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-08 04:53:18 +0000 |
commit | 14222d86785d89415c014dab294205fd186b7084 (patch) | |
tree | 8760046ac6e86fc86b3d570a2e7281dc6e42fafd /src/soc/intel/skylake/romstage | |
parent | 9970b61ad3049d87650cd7b4eb5f47d667098186 (diff) |
arch/x86: Change smm_subregion() prototype
Do this to avoid some amount of explicit typecasting
that would be required otherwise.
Change-Id: I5bc2c3c1dd579f7c6c3d3354c0691e4ba3c778e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/intel/skylake/romstage')
-rw-r--r-- | src/soc/intel/skylake/romstage/romstage_fsp20.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index b3781e2a65..221c6c41d5 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -173,9 +173,8 @@ asmlinkage void car_stage_entry(void) postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); if (CONFIG(HAVE_SMI_HANDLER)) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; - uintptr_t tseg_base; /* * Cache the TSEG region at the top of ram. This region is @@ -185,8 +184,7 @@ asmlinkage void car_stage_entry(void) * region for other purposes. */ smm_region(&smm_base, &smm_size); - tseg_base = (uintptr_t)smm_base; - postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, + postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); } |