diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-07-30 16:52:56 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-08-13 16:33:53 +0200 |
| commit | e33a1724b34d839fae16836a5bdde4d53a788c15 (patch) | |
| tree | c2633a17ff75eb31546a73c8e5fee689f8704dc7 /src/soc/intel/skylake/romstage | |
| parent | 14bb36c5ca08a646dd376d81199a6f22aa66b3d4 (diff) | |
skylake: fix serial port with new code base
Many Kconfig options changed in coreboot.org since
skylake was first started. Fix Kconfig option name
changes, and also provide a common option, UART_DEBUG
that can be selected to select all the necessary
options.
Note: It's still a requirement to manually unset the
8250IO option because that's unconditionally set.
BUG=chrome-os-partner:43419
BUG=chrome-os-partner:43463
BRANCH=None
TEST=Built glados. Booted into kernel. Kernel reboots somewhere.
Original-Change-Id: I9e6549ea0f1d6b9ffe64a73856ec87b5bc7b7091
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289951
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I0e6b492d7279cc35d4fb3ac17fd727177adce39d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11172
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/skylake/romstage')
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/romstage/uart.c | 11 |
2 files changed, 9 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 04ffa3e656..af9c78b585 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -50,7 +50,7 @@ void soc_pre_console_init(struct romstage_params *params) /* System Agent Early Initialization */ systemagent_early_init(); - if (IS_ENABLED(CONFIG_CONSOLE_UART8250MEM_32)) + if (IS_ENABLED(CONFIG_UART_DEBUG)) pch_uart_init(); } diff --git a/src/soc/intel/skylake/romstage/uart.c b/src/soc/intel/skylake/romstage/uart.c index afc8c63004..4dad8f662c 100644 --- a/src/soc/intel/skylake/romstage/uart.c +++ b/src/soc/intel/skylake/romstage/uart.c @@ -19,6 +19,7 @@ */ #include <arch/io.h> +#include <console/uart.h> #include <device/pci_def.h> #include <stdint.h> #include <soc/pci_devs.h> @@ -33,7 +34,7 @@ void pch_uart_init(void) { device_t dev = PCH_DEV_UART2; u32 tmp; - u8 *base = (u8 *)CONFIG_TTYS0_BASE; + u8 *base = (void *)uart_platform_base(CONFIG_UART_FOR_CONSOLE); /* Set configured UART2 base address */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)base); @@ -49,7 +50,11 @@ void pch_uart_init(void) SIO_REG_PPR_RESETS_IDMA; write32(base + SIO_REG_PPR_RESETS, tmp); - /* Set M and N divisor inputs and enable clock */ + /* + * Set M and N divisor inputs and enable clock. + * Main reference frequency to UART is: + * 120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz + */ tmp = read32(base + SIO_REG_PPR_CLOCK); tmp |= SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE | (SIO_REG_PPR_CLOCK_N_DIV << 16) | @@ -57,7 +62,7 @@ void pch_uart_init(void) write32(base + SIO_REG_PPR_CLOCK, tmp); /* Put UART2 in byte access mode for 16550 compatibility */ - if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL8250MEM_32)) + if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) pcr_andthenor32(PID_SERIALIO, R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, SIO_PCH_LEGACY_UART2); |