soc/skylake: do not rely on P2SB data to generate DRHD

The P2SB PCI device can be "hidden", which causes all sorts of
nightmares and bugs. Moreover, FSP tends to hide it, so finding
a good solution to this problem is impossible with FSP into the mix.

Since the values for IBDF and HBDF were already hardcoded as FSP
parameters, define them as macros and use these values directly to
generate the DRHD.

Change-Id: I7eb20182380b953a1842083e7a3c67919d6971b9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mimoja <coreboot@mimoja.de>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>

1 files changed, 4 insertions, 3 deletions

diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index ecd14289c2..002a284408 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -30,6 +30,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/romstage.h>
+#include <soc/systemagent.h>
 #include <string.h>
 #include <security/vboot/vboot_common.h>
 
@@ -247,9 +248,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 
 	if (!config->ignore_vtd) {
 		m_cfg->PchHpetBdfValid = 1;
-		m_cfg->PchHpetBusNumber = 250;
-		m_cfg->PchHpetDeviceNumber = 15;
-		m_cfg->PchHpetFunctionNumber = 0;
+		m_cfg->PchHpetBusNumber = V_P2SB_HBDF_BUS;
+		m_cfg->PchHpetDeviceNumber = V_P2SB_HBDF_DEV;
+		m_cfg->PchHpetFunctionNumber = V_P2SB_HBDF_FUN;
 	}
 }