diff options
| author | Robbie Zhang <robbie.zhang@intel.com> | 2017-02-13 12:07:53 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-02-18 06:30:53 +0100 |
| commit | e65affa2ed5d4fea584532c5cf27bf51ed1f56eb (patch) | |
| tree | c9a4ec6fa8e87ad482ee693c83603375d1572466 /src/soc/intel/skylake/romstage | |
| parent | ef7e98a2ac3449bc6a8d0cc73d7b54d41bc8bfa8 (diff) | |
soc/intel/skylake: add PrmrrSize to chip config
Prmrr configuration is supported by Kabylake FSP-M with UPD provided.
It is required as one of the SGX initialization steps in BIOS.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve, verified uncore PRMRR MSRs get programmed to set
size and boot.
Change-Id: I2b3dc7c92487505165ee429bd1a37bd60ceac8f3
Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-on: https://review.coreboot.org/18361
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/romstage')
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage_fsp20.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index e478890930..a4bb6849e4 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -139,6 +139,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) m_cfg->RMT = config->Rmt; m_cfg->DdrFreqLimit = config->DdrFreqLimit; m_cfg->VmxEnable = config->VmxEnable; + m_cfg->PrmrrSize = config->PrmrrSize; for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { if (config->PcieRpEnable[i]) mask |= (1<<i); |