diff options
author | Lijian Zhao <lijian.zhao@intel.com> | 2018-02-11 17:20:34 -0800 |
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committer | Subrata Banik <subrata.banik@intel.com> | 2018-02-16 03:27:36 +0000 |
commit | c303d741637a2190cd501e835ac07819d01bafea (patch) | |
tree | b502cb0853f7b6a609093e6b3a2a4498505f7c40 /src/soc/intel/skylake/romstage | |
parent | b716e550338e3da4dcbd9aedbd2c63695ffc8a99 (diff) |
soc/intel/common: Add generic PCR asl
Access to PCH Private Configuration Space Register can be addressed via
SBERG_BAR, the method is generic across several generations of Intel
SOC.
BUG=None
TEST=None
Change-Id: Iaf8c386824ee08cb93cb419ce3cdb2d3fe22a026
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/skylake/romstage')
0 files changed, 0 insertions, 0 deletions