diff options
| author | Nico Huber <nico.h@gmx.de> | 2018-11-21 00:11:35 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-18 20:24:50 +0000 |
| commit | 6275e345234383a249c8a44a777e1937219628fa (patch) | |
| tree | 5f4fc61d984ab4ac6b0fd420ffd6e1f09b5cfe73 /src/soc/intel/skylake/romstage | |
| parent | cd7873a28a311847bdd1fd7f74d2a6d0f66ede62 (diff) | |
soc/intel/skylake: Use real common code for VMX init
Use the common VMX implementation, and set IA32_FEATURE_CONTROL
lock bit per Kconfig *after* SGX is configured (as SGX also sets
bits on the IA32_FEATURE_CONTROL register).
As it is now correctly based on a Kconfig, the `VmxEnable` devicetree
setting vanishes.
Test: build/boot google/[chell,fizz], observe Virtualization enabled
under Windows 10 when VMX enabled and lock bit set.
Change-Id: Iea598cf74ba542a650433719f29cb5c9df700c0f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29682
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/romstage')
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage_fsp20.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 2a601588d6..6fe79f66f6 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -225,7 +225,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->RMT = config->Rmt; m_cfg->CmdTriStateDis = config->CmdTriStateDis; m_cfg->DdrFreqLimit = config->DdrFreqLimit; - m_cfg->VmxEnable = config->VmxEnable; + m_cfg->VmxEnable = IS_ENABLED(CONFIG_ENABLE_VMX); m_cfg->PrmrrSize = config->PrmrrSize; for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { if (config->PcieRpEnable[i]) |