diff options
| author | Nico Huber <nico.huber@secunet.com> | 2018-11-07 16:24:50 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-11-23 12:57:02 +0000 |
| commit | 2f1ef98bdcea248671bf2b5ad1547c1dcfec2c64 (patch) | |
| tree | 8191858420afaebd837bfca7d9637c8bceb00c15 /src/soc/intel/skylake/romstage | |
| parent | 6e8692e184e919c25feade059e30775798b640c2 (diff) | |
soc/intel/skylake: Drop FSP_CAR options
It's not implemented for Skylake, all combinations that try to enable it
either result in Kconfig or linker errors.
Move `config SKIP_FSP_CAR` into drivers/intel/fsp1_1 where it's
effective.
TEST=Built Intel/Kunimitsu (FSP1.1) and Intel/KBLRVP8 (FSP2.0) default
configs with and without this patch: binaries stay the same.
Change-Id: Iae0a2d2c7fd7a71ed24118564e6080c4789cda28
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/intel/skylake/romstage')
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index b194258228..e38ae519d7 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -83,10 +83,8 @@ void soc_memory_init_params(struct romstage_params *params, upd->SaGv = config->SaGv; upd->RMT = config->Rmt; upd->DdrFreqLimit = config->DdrFreqLimit; - if (IS_ENABLED(CONFIG_SKIP_FSP_CAR)) { - upd->FspCarBase = CONFIG_DCACHE_RAM_BASE; - upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE; - } + upd->FspCarBase = CONFIG_DCACHE_RAM_BASE; + upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE; } void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg, |