diff options
| author | Shaunak Saha <shaunak.saha@intel.com> | 2017-07-08 01:08:40 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-05 21:11:39 +0000 |
| commit | d3476809955ffb69447cc02a5ea893ebd1da3eb3 (patch) | |
| tree | 9ba3421063935064df6974b4879af4dc1b64fe83 /src/soc/intel/skylake/romstage/romstage_fsp20.c | |
| parent | f073872e22728fe8ade85022740af95cc129e9a5 (diff) | |
soc/intel/skylake: Add support in SKL for PMC common code
Change-Id: I3742f9c22d990edd918713155ae0bb1853663b6f
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/20499
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/romstage/romstage_fsp20.c')
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage_fsp20.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index cbf934e8bd..d4a5e34199 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -26,6 +26,7 @@ #include <device/pci_def.h> #include <fsp/util.h> #include <fsp/memmap.h> +#include <intelblocks/pmclib.h> #include <memory_info.h> #include <soc/intel/common/smbios.h> #include <soc/msr.h> @@ -119,9 +120,9 @@ asmlinkage void car_stage_entry(void) /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); - ps = fill_power_state(); + ps = pmc_get_power_state(); timestamp_add_now(TS_START_ROMSTAGE); - s3wake = ps->prev_sleep_state == ACPI_S3; + s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); if (!s3wake) |