soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC

Use the Broadwell implementation as the comparison base for Skylake.

BRANCH=none
BUG=None
TEST=None

Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10340
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

1 files changed, 13 insertions, 0 deletions

diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
new file mode 100644
index 0000000000..ae0f9806fd
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -0,0 +1,13 @@
+cpu_incs += $(src)/soc/intel/broadwell/romstage/cache_as_ram.inc
+
+romstage-y += cpu.c
+romstage-y += pch.c
+romstage-y += power_state.c
+romstage-y += raminit.c
+romstage-y += report_platform.c
+romstage-y += romstage.c
+romstage-y += smbus.c
+romstage-y += spi.c
+romstage-y += stack.c
+romstage-y += systemagent.c
+romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c