soc/intel/skylake: Use new power-failure-state API

Also move pmc_soc_restore_power_failure() which was guarded twice to
not be included in SMM, where the only call lives. Once all platforms
moved to the new API, it can be implemented in a central place, avoi-
ding the weak-function trap.

Change-Id: Ie72753764ecd876e6cb999fa0074d1114ae5efcf
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34725
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 28 insertions, 68 deletions

diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index c382131ebd..7bdc7f33b8 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -47,6 +47,32 @@ void pmc_set_disb(void)
 	pci_write_config32(dev, GEN_PMCON_A, disb_val);
 }
 
+/*
+ * Set which power state system will be after reapplying
+ * the power (from G3 State)
+ */
+void pmc_soc_set_afterg3_en(const bool on)
+{
+	uint8_t reg8;
+#if defined(__SIMPLE_DEVICE__)
+	const pci_devfn_t dev = PCH_DEV_PMC;
+#else
+	const struct device *const dev = PCH_DEV_PMC;
+#endif
+
+	reg8 = pci_read_config8(dev, GEN_PMCON_B);
+	if (on)
+		reg8 &= ~SLEEP_AFTER_POWER_FAIL;
+	else
+		reg8 |= SLEEP_AFTER_POWER_FAIL;
+	pci_write_config8(dev, GEN_PMCON_B, reg8);
+}
+
+void pmc_soc_restore_power_failure(void)
+{
+	pmc_set_power_failure_state(false);
+}
+
 #if ENV_RAMSTAGE
 /* Fill up PMC resource structure */
 int pmc_soc_get_resources(struct pmc_resource_config *cfg)
@@ -81,63 +107,6 @@ static const struct reg_script pmc_write1_to_clear_script[] = {
 	REG_SCRIPT_END
 };
 
-/*
- * Set which power state system will be after reapplying
- * the power (from G3 State)
- */
-static void pmc_set_afterg3(struct device *dev, int s5pwr)
-{
-	uint8_t reg8;
-
-	reg8 = pci_read_config8(dev, GEN_PMCON_B);
-
-	switch (s5pwr) {
-	case MAINBOARD_POWER_STATE_OFF:
-		reg8 |= 1;
-		break;
-	case MAINBOARD_POWER_STATE_ON:
-		reg8 &= ~1;
-		break;
-	case MAINBOARD_POWER_STATE_PREVIOUS:
-	default:
-		break;
-	}
-
-	pci_write_config8(dev, GEN_PMCON_B, reg8);
-}
-
-static void pch_power_options(struct device *dev)
-{
-	const char *state;
-
-	const int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
-
-	/*
-	 * Which state do we want to goto after g3 (power restored)?
-	 * 0 == S5 Soft Off
-	 * 1 == S0 Full On
-	 * 2 == Keep Previous State
-	 */
-	switch (pwr_on) {
-	case MAINBOARD_POWER_STATE_OFF:
-		state = "off";
-		break;
-	case MAINBOARD_POWER_STATE_ON:
-		state = "on";
-		break;
-	case MAINBOARD_POWER_STATE_PREVIOUS:
-		state = "state keep";
-		break;
-	default:
-		state = "undefined";
-	}
-	pmc_set_afterg3(dev, pwr_on);
-	printk(BIOS_INFO, "Set power %s after power failure.\n", state);
-
-	/* Set up GPE configuration. */
-	pmc_gpe_init();
-}
-
 static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable)
 {
 	uint32_t reg;
@@ -185,8 +154,8 @@ void pmc_soc_init(struct device *dev)
 
 	rtc_init();
 
-	/* Initialize power management */
-	pch_power_options(dev);
+	pmc_set_power_failure_state(true);
+	pmc_gpe_init();
 
 	/* Note that certain bits may be cleared from running script as
 	 * certain bit fields are write 1 to clear. */
@@ -201,15 +170,6 @@ void pmc_soc_init(struct device *dev)
 	reg_script_run_on_dev(dev, pmc_write1_to_clear_script);
 }
 
-/*
- * Set PMC register to know which state system should be after
- * power reapplied
- */
-void pmc_soc_restore_power_failure(void)
-{
-	pmc_set_afterg3(PCH_DEV_PMC, CONFIG_MAINBOARD_POWER_FAILURE_STATE);
-}
-
 static void pm1_enable_pwrbtn_smi(void *unused)
 {
 	/*