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| author | Andrey Petrov <andrey.petrov@intel.com> | 2016-07-18 00:15:41 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-19 21:03:03 +0200 |
| commit | 3a94a3ba5b238067f382d07f92c57373003b79cc (patch) | |
| tree | 37e2b5da73fef0646590ac13306871a25b92dbed /src/soc/intel/skylake/pcr.c | |
| parent | 1b1d4b7ae653e56ec7cdeec438487ae7ded0e62a (diff) | |
drivers/intel/fsp2_0: Split reset handling logic
FSP 2.0 spec only defines 2 reset request (COLD, WARM) exit codes. The
rest 6 codes are platform-specific and may vary. Modify helper function
so that only basic resets are handled and let SoC deal with the rest.
Change-Id: Ib2f446e0449301407b135933a2088bcffc3ac32a
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15730
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/skylake/pcr.c')
0 files changed, 0 insertions, 0 deletions