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authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-07-26 08:53:59 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-06 20:43:17 +0100
commitb4a45dcf9d442b311dec7396a55be917713a0d15 (patch)
tree4b287fac6d041096a3709d3707533ac52cfca78e /src/soc/intel/skylake/pcie.c
parentd45114ff59284cebc0c03821cc4d7782ca3bacf8 (diff)
intel PCI ops: Remove explicit PCI MMCONF access
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. Change-Id: If62537475eb67b7ecf85f2292a2a954a41bc18d1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17545 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/pcie.c')
-rw-r--r--src/soc/intel/skylake/pcie.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/pcie.c b/src/soc/intel/skylake/pcie.c
index 719abf33e3..d3eecff585 100644
--- a/src/soc/intel/skylake/pcie.c
+++ b/src/soc/intel/skylake/pcie.c
@@ -75,7 +75,7 @@ static void pch_pcie_init(struct device *dev)
static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int off)
{
/* Set max snoop and non-snoop latency for the SOC */
- pci_mmio_write_config32(dev, off, 0x10031003);
+ pci_write_config32(dev, off, 0x10031003);
}
static struct pci_operations pcie_ops = {