diff options
| author | Rex-BC Chen <rex-bc.chen@mediatek.com> | 2022-07-28 16:38:53 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-08-03 16:40:20 +0000 |
| commit | f9009dde545bc96840f381afc3170818a0d91e29 (patch) | |
| tree | d5b0a1c96931c716da27ba3e062f73490e9b897b /src/soc/intel/skylake/irq.c | |
| parent | d9e568a0464796b0d5e6209f4c5e3d7ed42e59b2 (diff) | |
mb/google/geralt: Configure GPIOs
Configure ChromeOS specific GPIOs:
- Open-drain pins to high-z mode:
GPIO_EC_AP_INT_ODL, GPIO_GSC_AP_INT_ODL and GPIO_WP_ODL.
- GPO mode:
GPIO_AP_EC_WARM_RST_REQ, GPIO_EN_SPKR and GPIO_XHCI_INIT_DONE.
This patch is based on MT8188G_GPIO_Formal_Application_Spec_V0.3.
TEST=build pass
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I84d3f62ec8a3966fe1982d5d4cf6ff270450d4bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66274
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/irq.c')
0 files changed, 0 insertions, 0 deletions