soc/intel/skylake: switch to common ACPI code

Use the common ACPI code to reduce code duplication.

After this change, `PSS_MAX_ENTRIES` is honored correctly in P-state
table generation (as of commit c2540a9) and the number reduces from 10
to 7 entries.

Also, remnants of P_BLK support missed in CB:58096 will vanish.

Tested on google/fizz: no errors in dmesg, ACPI tables remain the same
(except PSS, as mentioned above).

Change-Id: I1ec804ae4006a2d9b69c0d93a658eb3b84d60b40
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>

4 files changed, 8 insertions, 21 deletions

diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h
deleted file mode 100644
index 683a50490a..0000000000
--- a/src/soc/intel/skylake/include/soc/acpi.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _SOC_ACPI_H_
-#define _SOC_ACPI_H_
-
-#include <acpi/acpi.h>
-
-/* P-state configuration */
-#define PSS_MAX_ENTRIES			8
-#define PSS_RATIO_STEP			2
-#define PSS_LATENCY_TRANSITION		10
-#define PSS_LATENCY_BUSMASTER		10
-
-/* Return the selected ACPI SCI IRQ */
-int acpi_sci_irq(void);
-unsigned long acpi_madt_irq_overrides(unsigned long current);
-unsigned long northbridge_write_acpi_tables(const struct device *,
-	unsigned long current, struct acpi_rsdp *);
-
-#endif /* _SOC_ACPI_H_ */
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index a57772446e..f0ce146562 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -141,6 +141,12 @@
 
 #define PRSTS		0x10
 
+/* P-state configuration */
+#define PSS_MAX_ENTRIES		8
+#define PSS_RATIO_STEP		2
+#define PSS_LATENCY_TRANSITION	10
+#define PSS_LATENCY_BUSMASTER	10
+
 struct chipset_power_state {
 	uint16_t pm1_sts;
 	uint16_t pm1_en;
diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h
index 8fe3f83cad..165d57170e 100644
--- a/src/soc/intel/skylake/include/soc/pmc.h
+++ b/src/soc/intel/skylake/include/soc/pmc.h
@@ -59,6 +59,8 @@
 #define ETR3			0xac
 #define  ETR3_CF9LOCK		(1 << 31)
 #define  ETR3_CF9GR		(1 << 20)
+#define SCI_IRQ_ADJUST		0
+#define IRQ_REG			ACTL
 
 /* Memory mapped IO registers in PMC */
 #define S3_PWRGATE_POL		0x28
diff --git a/src/soc/intel/skylake/include/soc/ramstage.h b/src/soc/intel/skylake/include/soc/ramstage.h
index 02d53a1e17..a5e6930bec 100644
--- a/src/soc/intel/skylake/include/soc/ramstage.h
+++ b/src/soc/intel/skylake/include/soc/ramstage.h
@@ -15,6 +15,5 @@
 void mainboard_silicon_init_params(FSP_S_CONFIG *params);
 void soc_init_pre_device(void *chip_info);
 void soc_irq_settings(FSP_SIL_UPD *params);
-const char *soc_acpi_name(const struct device *dev);
 
 #endif