soc/intel/skylake: Make use of common SMM code for SKL

This patch ensures skylake soc is using common SMM code
from intel common block.

TEST=Build and boot soraka/eve

Change-Id: I8163dc7e18bb417e8c18a12628988959c128b3df
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/22826
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 21 insertions, 26 deletions

diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index da6b2af110..8bc4d8dfe4 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -69,9 +69,4 @@ typedef struct global_nvs_t {
 } __packed global_nvs_t;
 check_member(global_nvs_t, chromeos, 0x100);
 
-#if ENV_SMM
-/* Used in SMM to find the ACPI GNVS address */
-global_nvs_t *smm_get_gnvs(void);
-#endif
-
 #endif
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index e904658397..b7d6446543 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -23,6 +23,7 @@
 #include <soc/gpe.h>
 #include <soc/iomap.h>
 #include <soc/pmc.h>
+#include <soc/smbus.h>
 
 /* ACPI_BASE_ADDRESS / PMBASE */
 
@@ -135,12 +136,25 @@
 
 #define GBLRST_CAUSE0_THERMTRIP	(1 << 5)
 
+/*
+ * Enable SMI generation:
+ *  - on APMC writes (io 0xb2)
+ *  - on writes to SLP_EN (sleep states)
+ *  - on writes to GBL_RLS (bios commands)
+ *  - on eSPI events (does nothing on LPC systems)
+ * No SMIs:
+ *  - on microcontroller writes (io 0x62/0x66)
+ *  - on TCO events
+ */
+#define ENABLE_SMI_PARAMS \
+	(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS)
+
 /* This is defined as ETR3 in EDS. We named it as ETR here for consistency */
-#define ETR			0xac
-#define  CF9_LOCK         (1 << 31)
-#define  CF9_GLB_RST      (1 << 20)
+#define ETR		0xac
+#define  CF9_LOCK	(1 << 31)
+#define  CF9_GLB_RST	(1 << 20)
 
-#define PRSTS                   0x10
+#define PRSTS		0x10
 
 struct chipset_power_state {
 	uint16_t pm1_sts;
diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h
index ad5ae2611c..aeaf1d9ea2 100644
--- a/src/soc/intel/skylake/include/soc/smbus.h
+++ b/src/soc/intel/skylake/include/soc/smbus.h
@@ -4,7 +4,7 @@
  * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
  * Copyright (C) 2009 coresystems GmbH
  * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2017 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -29,6 +29,7 @@
 
 /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
 #define TCO1_STS			0x04
+#define  TCO_TIMEOUT			(1 << 3)
 #define TCO2_STS			0x06
 #define TCO2_STS_SECOND_TO		0x02
 #define TCO2_STS_BOOT			0x04
diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h
index 06c4aacd3d..0f857e05ce 100644
--- a/src/soc/intel/skylake/include/soc/smm.h
+++ b/src/soc/intel/skylake/include/soc/smm.h
@@ -21,6 +21,7 @@
 #include <compiler.h>
 #include <cpu/x86/msr.h>
 #include <fsp/memmap.h>
+#include <intelblocks/smihandler.h>
 #include <soc/gpio.h>
 
 struct ied_header {
@@ -48,12 +49,6 @@ struct smm_relocation_params {
 	int smm_save_state_in_msrs;
 };
 
-/* Mainboard handler for GPI SMIs*/
-void mainboard_smi_gpi_handler(const struct gpi_status *sts);
-
-/* Mainboard handler for eSPI SMIs */
-void mainboard_smi_espi_handler(void);
-
 #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
 void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
 				uintptr_t staggered_smbase);
@@ -61,14 +56,6 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 		size_t *smm_save_state_size);
 void smm_initialize(void);
 void smm_relocate(void);
-
-/*
- * The initialization of the southbridge is split into 2 compoments. One is
- * for clearing the state in the SMM registers. The other is for enabling
- * SMIs.
- */
-void southbridge_smm_clear_state(void);
-void southbridge_smm_enable_smi(void);
 #else	/* CONFIG_HAVE_SMI_HANDLER */
 static inline void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
 				uintptr_t staggered_smbase) {}
@@ -77,8 +64,6 @@ static inline void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 static inline void smm_initialize(void) {}
 
 static inline void smm_relocate(void) {}
-static inline void southbridge_smm_clear_state(void) {}
-static inline void southbridge_smm_enable_smi(void) {}
 #endif	/* CONFIG_HAVE_SMI_HANDLER */
 
 #endif