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authorBarnali Sarkar <barnali.sarkar@intel.com>2017-05-04 18:02:17 +0530
committerAaron Durbin <adurbin@chromium.org>2017-06-09 19:24:58 +0200
commit0a203d13f672b5cf12a56eaecfbcbe2e081f18ed (patch)
tree7d1d1e101e602102c528851769de3229095c2744 /src/soc/intel/skylake/include
parent19b546f48cb790285afa366dceab9da62cbbe4ac (diff)
soc/intel/skylake: Use CPU common library code
This patch makes SOC files to use common/block/cpu/cpulib.c file's helper functions. Change-Id: I6af56564c6f488f58173ba0beda6912763706f9f Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19566 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
-rw-r--r--src/soc/intel/skylake/include/soc/cpu.h1
-rw-r--r--src/soc/intel/skylake/include/soc/msr.h16
2 files changed, 0 insertions, 17 deletions
diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h
index f6803c9e04..7bfd8bae2b 100644
--- a/src/soc/intel/skylake/include/soc/cpu.h
+++ b/src/soc/intel/skylake/include/soc/cpu.h
@@ -59,7 +59,6 @@
/* Configure power limits for turbo mode */
void set_power_limits(u8 power_limit_1_time);
-int cpu_config_tdp_levels(void);
/* CPU identification */
u32 cpu_family_model(void);
diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h
index 36eefdb7b0..98f25a153e 100644
--- a/src/soc/intel/skylake/include/soc/msr.h
+++ b/src/soc/intel/skylake/include/soc/msr.h
@@ -21,9 +21,6 @@
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_BIOS_UPGD_TRIG 0x7a
-#define MSR_FLEX_RATIO 0x194
-#define FLEX_RATIO_LOCK (1 << 20)
-#define FLEX_RATIO_EN (1 << 16)
#define IA32_THERM_INTERRUPT 0x19b
#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
#define ENERGY_POLICY_PERFORMANCE 0
@@ -31,13 +28,8 @@
#define ENERGY_POLICY_POWERSAVE 15
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
#define PRMRR_PHYS_BASE_MSR 0x1f4
-#define PRMRR_PHYS_MASK_MSR 0x1f5
-#define PRMRR_PHYS_MASK_LOCK (1 << 10)
-#define PRMRR_PHYS_MASK_VALID (1 << 11)
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define MSR_LT_LOCK_MEMORY 0x2e7
-#define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4
-#define UNCORE_PRMRR_PHYS_MASK_MSR 0x2f5
#define MSR_SGX_OWNEREPOCH0 0x300
#define MSR_SGX_OWNEREPOCH1 0x301
#define MSR_VR_CURRENT_CONFIG 0x601
@@ -46,12 +38,4 @@
#define MSR_PP0_POWER_LIMIT 0x638
#define MSR_PP1_POWER_LIMIT 0x640
-/* SMM save state MSRs */
-#define SMBASE_MSR 0xc20
-#define IEDBASE_MSR 0xc22
-
-/* MTRR_CAP_MSR bits */
-#define SMRR_SUPPORTED (1<<11)
-#define PRMRR_SUPPORTED (1<<12)
-
#endif