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authorSubrata Banik <subrata.banik@intel.com>2017-02-03 19:05:27 +0530
committerAaron Durbin <adurbin@chromium.org>2017-06-09 19:26:55 +0200
commitf004f66ca7b0c428c04d6025738319187cf911fe (patch)
tree018b0fedb7981caca6e5f207a10e8351bc25c85b /src/soc/intel/skylake/include
parent0a203d13f672b5cf12a56eaecfbcbe2e081f18ed (diff)
soc/intel/skylake: Enable ACPI PM timer emulation on all CPUs
This patch enables ACPI timer emulation on all the logical cpus. BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Verify MSR 0x121 gets programmed on all logical cpus during coreboot MP Init. Change-Id: I2246cdfe1f60fd359b0a0eda89b4a45b5554dc4a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18288 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
-rw-r--r--src/soc/intel/skylake/include/soc/cpu.h3
-rw-r--r--src/soc/intel/skylake/include/soc/msr.h4
2 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h
index 7bfd8bae2b..6419bf8506 100644
--- a/src/soc/intel/skylake/include/soc/cpu.h
+++ b/src/soc/intel/skylake/include/soc/cpu.h
@@ -51,6 +51,9 @@
#define C9_POWER 0xc8
#define C10_POWER 0xc8
+/* Common Timer Copy (CTC) frequency - 19.2MHz. */
+#define CTC_FREQ 19200000
+
#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
(((1 << ((base)*5)) * (limit)) / 1000)
#define C_STATE_LATENCY_FROM_LAT_REG(reg) \
diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h
index 98f25a153e..bb4b8e72ac 100644
--- a/src/soc/intel/skylake/include/soc/msr.h
+++ b/src/soc/intel/skylake/include/soc/msr.h
@@ -21,6 +21,10 @@
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_BIOS_UPGD_TRIG 0x7a
+#define MSR_EMULATE_PM_TIMER 0x121
+#define EMULATE_PM_TMR_EN (1 << 16)
+#define EMULATE_DELAY_OFFSET_VALUE 20
+#define EMULATE_DELAY_VALUE 0x13
#define IA32_THERM_INTERRUPT 0x19b
#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
#define ENERGY_POLICY_PERFORMANCE 0