soc/intel/common: remove chipset specific calls

The report_platform_info() and set_max_freq() are not being
used similarly on skylake and braswell. With the addition
of other SoCs I suspect a similar pattern will emerge. Instead
of having weak functions to ensure things link with the hardcoded
policy push these calls into their respective SoC homes.

For parity, both skylake and braswell were updated to be consistent
with the same calls prior to this patch.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados. Built braswell.

Original-Change-Id: I3371d09aff0629503254296955fef28d35754a38
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/303334
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: I2de33632ed127cac52d7075cbad95cd6387a1b46
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11815
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h
index d1c846b045..a88de66441 100644
--- a/src/soc/intel/skylake/include/soc/romstage.h
+++ b/src/soc/intel/skylake/include/soc/romstage.h
@@ -29,6 +29,8 @@ void systemagent_early_init(void);
 void pch_early_init(void);
 void pch_uart_init(void);
 void intel_early_me_status(void);
+void report_platform_info(void);
+void set_max_freq(void);
 
 void enable_smbus(void);
 int smbus_read_byte(unsigned device, unsigned address);