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authorSubrata Banik <subrata.banik@intel.com>2017-06-02 17:52:44 +0530
committerMartin Roth <martinroth@google.com>2017-06-06 19:42:17 +0200
commitc2165671b0ad0715a7cd1183390ca1b2c301d336 (patch)
treeff5c4512ff78a874acc65b03a450ab76ae8e2c70 /src/soc/intel/skylake/include
parent54fd92bc343da755b53bc290573ca59e63890d07 (diff)
soc/intel/skylake: Use PCI IDs from device/pci_ids.h
Remove PCI IDs inclusion from soc header rather referring those from device/pci_ids.h. Change-Id: I490da3e336fb6f8194d5fba800132f550ed5ab37 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
-rw-r--r--src/soc/intel/skylake/include/soc/pch.h14
-rw-r--r--src/soc/intel/skylake/include/soc/systemagent.h21
2 files changed, 0 insertions, 35 deletions
diff --git a/src/soc/intel/skylake/include/soc/pch.h b/src/soc/intel/skylake/include/soc/pch.h
index 9602f10d31..800e0de0e7 100644
--- a/src/soc/intel/skylake/include/soc/pch.h
+++ b/src/soc/intel/skylake/include/soc/pch.h
@@ -21,20 +21,6 @@
#include <device/device.h>
#include <rules.h>
-/* PCH (SunRisePoint LP) */
-#define PCH_SPT_LP_SAMPLE 0x9d41
-#define PCH_SPT_LP_U_BASE 0x9d43
-#define PCH_SPT_LP_U_PREMIUM 0x9d48
-#define PCH_SPT_LP_Y_PREMIUM 0x9d46
-#define PCH_SPT_H_C236 0xa150
-#define PCH_SPT_H_PREMIUM 0xa14e
-#define PCH_SPT_H_QM170 0xa14d
-#define PCH_KBL_LP_Y_PREMIUM_HDCP22 0x9d4b
-#define PCH_KBL_LP_U_PREMIUM_HDCP22 0x9d4e
-#define PCH_LP_SUPER_SKU 0x9d51
-#define PCH_KBL_LP_U_PREMIUM 0x9d58
-#define PCH_KBL_LP_Y_PREMIUM 0x9d56
-
u8 pch_revision(void);
u16 pch_type(void);
void pch_log_state(void);
diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h
index 4b26387e1a..012a8755d1 100644
--- a/src/soc/intel/skylake/include/soc/systemagent.h
+++ b/src/soc/intel/skylake/include/soc/systemagent.h
@@ -23,27 +23,6 @@
#define SA_IGD_OPROM_VENDEV 0x80860406
-#define IGD_SKYLAKE_GT1_SULTM 0x1906
-#define IGD_SKYLAKE_GT2_SULXM 0x191E
-#define IGD_SKYLAKE_GT2_SULTM 0x1916
-#define IGD_SKYLAKE_GT2_SHALM 0x191B
-#define IGD_SKYLAKE_GT4_SHALM 0x193D
-#define IGD_KABYLAKE_GT1_SULTM 0x5906
-#define IGD_KABYLAKE_GT2_SULXM 0x591E
-#define IGD_KABYLAKE_GT2_SULTM 0x5916
-#define IGD_KABYLAKE_GT2_SULTMR 0x5917
-#define IGD_KABYLAKE_GT2_SHALM 0x591B
-
-#define MCH_SKYLAKE_ID_U 0x1904
-#define MCH_SKYLAKE_ID_Y 0x190c
-#define MCH_SKYLAKE_ID_ULX 0x1924
-#define MCH_SKYLAKE_ID_H 0x1910
-#define MCH_SKYLAKE_ID_H_EM 0x1918
-#define MCH_KABYLAKE_ID_U 0x5904
-#define MCH_KABYLAKE_ID_Y 0x590c
-#define MCH_KABYLAKE_ID_H 0x5910
-#define MCH_KABYLAKE_ID_U_R 0x5914
-
/* Device 0:0.0 PCI configuration space */
#define EPBAR 0x40