src/soc/intel/common/block/cse: Make hfsts1 common & add helper functions

Host FW status 1 (FWSTS1/HFSTS1) register definition is common across SoCs,
hence move it to common. Also add below helper function,

* wait_cse_sec_override_mode() - Polls ME status for "HECI_OP_MODE_SEC_OVERRIDE".
  It's a special CSE mode, the mode ensures CSE does not trigger any
  spi cycles to CSE region.

* set_host_ready() - Clears reset state from host CSR.

TEST=Verified CSE recover mode on CML RVP & Hatch board

Change-Id: Id5c12b7abdb27c38af74ea6ee568b42ec74bcb3c
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>

1 files changed, 0 insertions, 24 deletions

diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h
index fbe5033d7c..ef84f59686 100644
--- a/src/soc/intel/skylake/include/soc/me.h
+++ b/src/soc/intel/skylake/include/soc/me.h
@@ -47,30 +47,6 @@
 #define  ME_HFS_POWER_SOURCE_AC 1
 #define  ME_HFS_POWER_SOURCE_DC 2
 
-union me_hfs {
-	u32 data;
-	struct {
-	u32 working_state: 4;
-	u32 mfg_mode: 1;
-	u32 fpt_bad: 1;
-	u32 operation_state: 3;
-	u32 fw_init_complete: 1;
-	u32 ft_bup_ld_flr: 1;
-	u32 update_in_progress: 1;
-	u32 error_code: 4;
-	u32 operation_mode: 4;
-	u32 reset_count: 4;
-	u32 boot_options_present: 1;
-	u32 reserved1: 1;
-	u32 bist_test_state: 1;
-	u32 bist_reset_request: 1;
-	u32 current_power_source: 2;
-	u32 d3_support_valid: 1;
-	u32 d0i3_support_valid: 1;
-	} __packed fields;
-};
-
-#define PCI_ME_HFSTS2		0x48
 /* Infrastructure Progress Values */
 #define  ME_HFS2_PHASE_ROM		0
 #define  ME_HFS2_PHASE_UKERNEL		2