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authorMaxim Polyakov <max.senia.poliak@gmail.com>2019-04-25 12:32:15 +0300
committerPatrick Georgi <pgeorgi@google.com>2019-04-29 12:20:43 +0000
commit5806665059f1483665c1b2a8ad386e1e90265dcd (patch)
treee4e50f98247a37c6cbb18042470eed77b986b27c /src/soc/intel/skylake/include
parent5a69491a01b6fe32a975aee557348acc84fc7a40 (diff)
soc/skl: set IGD resources only if device is enabled
If the Intel IGD device pci 02.0 is disabled or undefined in the device tree, then internal graphics pre-allocated memory and GFX-VT MMIO memory for virtualization won`t be allocated in the SoC address space. Thus, patch resolves the FSP-S hang problem on Skylake/ Kaby Lake processors when the IGD device is disabled. This should provide to run FSP 2.0-based coreboot on these CPUs families without integrated graphics card. The following boards were used for testing: - Asrock H110M-DVS board (desktop i5-6600) & NVIDIA GTX 1060 as external GPU. Virtualization and GFX 3D acceleration with nouveau driver still works well (tested on VirtualBox 5.1.38 with Ubuntu 18.04.1 as guest and host OS) - Intel KBL-R U RVP board (mobile i5-8350u) without GFX. Payload: tianocore edk2-stable201811-216-g51be9d0. Change-Id: Id7a0cba582d83e3fe7e8d20342ee219cdd369a53 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32467 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
-rw-r--r--src/soc/intel/skylake/include/soc/systemagent.h14
1 files changed, 11 insertions, 3 deletions
diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h
index 8e53f54b75..d7dec65f58 100644
--- a/src/soc/intel/skylake/include/soc/systemagent.h
+++ b/src/soc/intel/skylake/include/soc/systemagent.h
@@ -48,9 +48,17 @@
bool soc_is_vtd_capable(void);
-static const struct sa_mmio_descriptor soc_vtd_resources[] = {
- { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" },
- { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" },
+static const struct sa_mmio_descriptor soc_gfxvt_mmio_descriptor = {
+ GFXVTBAR,
+ GFXVT_BASE_ADDRESS,
+ GFXVT_BASE_SIZE,
+ "GFXVTBAR"
};
+static const struct sa_mmio_descriptor soc_vtvc0_mmio_descriptor = {
+ VTVC0BAR,
+ VTVC0_BASE_ADDRESS,
+ VTVC0_BASE_SIZE,
+ "VTVC0BAR"
+};
#endif