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authorBora Guvendik <bora.guvendik@intel.com>2017-04-11 16:05:23 -0700
committerMartin Roth <martinroth@google.com>2017-04-28 16:32:20 +0200
commit43c31096965a05bc5ac0da0a7fb701167e9fb68e (patch)
tree700087ca2dce499392d32072bdbdf0f5e2d14efa /src/soc/intel/skylake/include
parent33117ec6012fa78765209593e9ab1f4a07812d83 (diff)
soc/intel/skylake: Use ITSS common code
This patch uses common ITSS library to setup itss irq. Change-Id: Ibe65a92f1604277bec229c67f4375b6636c0972d Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/19244 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
-rw-r--r--src/soc/intel/skylake/include/soc/itss.h24
1 files changed, 3 insertions, 21 deletions
diff --git a/src/soc/intel/skylake/include/soc/itss.h b/src/soc/intel/skylake/include/soc/itss.h
index 0681e9d5dd..5ff9bb1e55 100644
--- a/src/soc/intel/skylake/include/soc/itss.h
+++ b/src/soc/intel/skylake/include/soc/itss.h
@@ -16,26 +16,8 @@
#ifndef SOC_INTEL_SKL_ITSS_H
#define SOC_INTEL_SKL_ITSS_H
-/* Max PXRC registers in ITSS*/
-#define MAX_PXRC_CONFIG 0x08
-
-/* PIRQA Routing Control Register*/
-#define PCR_ITSS_PIRQA_ROUT 0x3100
-/* PIRQB Routing Control Register*/
-#define PCR_ITSS_PIRQB_ROUT 0x3101
-/* PIRQC Routing Control Register*/
-#define PCR_ITSS_PIRQC_ROUT 0x3102
-/* PIRQD Routing Control Register*/
-#define PCR_ITSS_PIRQD_ROUT 0x3103
-/* PIRQE Routing Control Register*/
-#define PCR_ITSS_PIRQE_ROUT 0x3104
-/* PIRQF Routing Control Register*/
-#define PCR_ITSS_PIRQF_ROUT 0x3105
-/* PIRQG Routing Control Register*/
-#define PCR_ITSS_PIRQG_ROUT 0x3106
-/* PIRQH Routing Control Register*/
-#define PCR_ITSS_PIRQH_ROUT 0x3107
-/* ITSS Power reduction control */
-#define PCR_ITSS_ITSSPRC 0x3300
+#define ITSS_MAX_IRQ 119
+#define IRQS_PER_IPC 32
+#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
#endif /* SOC_INTEL_SKL_ITSS_H */