diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-07-30 10:20:53 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-08-14 15:15:28 +0200 |
| commit | 3b6c398bf4923dfabb486825116783d5208d3035 (patch) | |
| tree | 0342c299be30f4fec594a8bd055867bc5d424564 /src/soc/intel/skylake/include | |
| parent | 85654a66504f2c87f129d3c414995be4b6cdc09f (diff) | |
skylake: enumerate the SMI status fields
Provide #defines for the bit fields in the SMI status register.
This allows for one to set the callback accordingly without
hard coding the index.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I3e61d431717c725748409ef5b543ad2eb82955c4
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289802
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I1a91f2c8b903de4297aaa66f5c6ff15f1b9c54f6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11184
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pm.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 0475e20d78..9409ba2184 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -72,6 +72,30 @@ #define EOS (1 << 1) #define GBL_SMI_EN (1 << 0) #define SMI_STS 0x34 +#define SMI_STS_BITS 32 +#define XHCI_SMI_STS_BIT 31 +#define ME_SMI_STS_BIT 30 +#define SERIAL_IO_SMI_STS_BIT 29 +#define ESPI_SMI_STS_BIT 28 +#define GPIO_UNLOCK_SMI_STS_BIT 27 +#define SPI_SMI_STS_BIT 26 +#define SCC_SMI_STS_BIT 25 +#define MONITOR_STS_BIT 21 +#define PCI_EXP_SMI_STS_BIT 20 +#define SMBUS_SMI_STS_BIT 16 +#define SERIRQ_SMI_STS_BIT 15 +#define PERIODIC_STS_BIT 14 +#define TCO_STS_BIT 13 +#define DEVMON_STS_BIT 12 +#define MCSMI_STS_BIT 11 +#define GPIO_STS_BIT 10 +#define GPE0_STS_BIT 9 +#define PM1_STS_BIT 8 +#define SWSMI_TMR_STS_BIT 6 +#define APM_STS_BIT 5 +#define SMI_ON_SLP_EN_STS_BIT 4 +#define LEGACY_USB_STS_BIT 3 +#define BIOS_STS_BIT 2 #define UPWRC 0x3c #define UPWRC_WS (1 << 8) #define UPWRC_WE (1 << 1) |