diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-12-14 16:44:26 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-01-18 12:12:12 +0100 |
| commit | df21440d682403aec56912a44fb7c4bffd507e8e (patch) | |
| tree | 803fb7523b1e68de5496cb66e3315cc9463e5a47 /src/soc/intel/skylake/include | |
| parent | ae34cae4fe12d9e6b5a70b577d181bb813aa3840 (diff) | |
intel/skylake: provide default VR configuration
FSP 1.8.0 will do nothing with the VR settings if VrConfigEnable is
non-zero. That behavior is not desired because it's not clear what
the behavior will be for various processor SKUs. Instead provide
default values for the VR config. Note that PSI3 and PSI4 are not
enabled for those defaults.
BUG=chrome-os-partner:48466
BRANCH=None
TEST=Built and booted glados.
Change-Id: I02cb5fbdd4549cc827a0b0e4006bc21da4593b55
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a68c53e0fdf15584270dfafc679a22319f497d17
Original-Change-Id: I82b1d1da2cfa3c83ccc6a981e30ffac6fb6c8c4b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/318263
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12983
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/vr_config.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h index 926ddf1a16..204b848a57 100644 --- a/src/soc/intel/skylake/include/soc/vr_config.h +++ b/src/soc/intel/skylake/include/soc/vr_config.h @@ -23,6 +23,8 @@ #ifndef _SOC_VR_CONFIG_H_ #define _SOC_VR_CONFIG_H_ +#include <fsp/soc_binding.h> + struct vr_config { /* @@ -61,6 +63,8 @@ struct vr_config { int voltage_limit; }; +#define VR_CFG_AMP(i) ((i) * 4) + /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced @@ -74,4 +78,7 @@ enum vr_domain{ NUM_VR_DOMAINS }; +void fill_vr_domain_config(SILICON_INIT_UPD *params, int domain, + const struct vr_config *cfg); + #endif |