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authorFurquan Shaikh <furquan@chromium.org>2017-08-17 18:28:41 -0700
committerFurquan Shaikh <furquan@google.com>2017-08-19 00:33:04 +0000
commitaeb2d64c85ca2c3a77f50d57e3a92f6fc0a5c2d3 (patch)
tree1b0e09b0ff072bfeb3d300c709b24d1037362a08 /src/soc/intel/skylake/include
parentaef8542d810b737fe2653dcca1d9566292b3b65d (diff)
soc/intel/skylake: Enable power button SMI when jumping to payload
Instead of enabling power button SMI unconditionally, add a boot state handler to enable power button SMI just before jumping to payload. This ensures that: 1. We do not respond to power button SMI until we know that coreboot is done. 2. On resume, there is no need to enable power button SMI. This avoids any power button presses during resume path from triggering a shutdown. BUG=b:64811381 Change-Id: Icc52dc0103555602c23e09660bc38bb4bfddbc11 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/skylake/include')
-rw-r--r--src/soc/intel/skylake/include/soc/pm.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index 67b1f438b6..1e4520e687 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -159,6 +159,8 @@ void disable_pm1_control(uint32_t mask);
/* PM1 */
uint16_t clear_pm1_status(void);
void enable_pm1(uint16_t events);
+void update_pm1_enable(uint16_t events);
+uint16_t read_pm1_enable(void);
uint32_t clear_smi_status(void);
/* SMI */