diff options
| author | Pratik Prajapati <pratikkumar.v.prajapati@intel.com> | 2017-06-12 23:02:36 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-07-10 17:16:26 +0000 |
| commit | a04aa3d5662149b70f31e0e6584bd8c6087b5f3b (patch) | |
| tree | 9886be703d858b08525743fe0bdcf2b921d9b07f /src/soc/intel/skylake/include | |
| parent | 8c94e14a0c0e77061d8fb879f4bf7bc1347b38d2 (diff) | |
sgx: Move SGX code to intel/common/block
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX controls building. The SGX feature
is still enabled from devicetree.cb. As of now this SGX init supports
only KBL (SKL not tested). Support of SGX for new SOCs would be added
incrementally in this common code base.
Change-Id: I0fbba364b7342e686a2287ea1a910ef9a4eed595
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/20173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/cpu.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/msr.h | 4 |
2 files changed, 0 insertions, 5 deletions
diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 059367aaa9..8073fcdded 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -56,6 +56,5 @@ void set_power_limits(u8 power_limit_1_time); u32 cpu_family_model(void); u32 cpu_stepping(void); int cpu_is_ult(void); -void configure_sgx(const void *microcode_patch); #endif diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index bb4b8e72ac..81b6cc9de1 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -20,7 +20,6 @@ #include <intelblocks/msr.h> #define MSR_PIC_MSG_CONTROL 0x2e -#define MSR_BIOS_UPGD_TRIG 0x7a #define MSR_EMULATE_PM_TIMER 0x121 #define EMULATE_PM_TMR_EN (1 << 16) #define EMULATE_DELAY_OFFSET_VALUE 20 @@ -31,11 +30,8 @@ #define ENERGY_POLICY_NORMAL 6 #define ENERGY_POLICY_POWERSAVE 15 #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 -#define PRMRR_PHYS_BASE_MSR 0x1f4 #define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_LT_LOCK_MEMORY 0x2e7 -#define MSR_SGX_OWNEREPOCH0 0x300 -#define MSR_SGX_OWNEREPOCH1 0x301 #define MSR_VR_CURRENT_CONFIG 0x601 #define MSR_VR_MISC_CONFIG 0x603 #define MSR_VR_MISC_CONFIG2 0x636 |