diff options
| author | Barnali Sarkar <barnali.sarkar@intel.com> | 2017-06-13 20:22:33 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-06-23 15:48:38 +0000 |
| commit | 73273860516721f917358ad620f7fbc771ca9430 (patch) | |
| tree | a6d4148941aa83d66dc154d2c73dc28ecc065b01 /src/soc/intel/skylake/include | |
| parent | 91d38a5b0e070e75f32b30cb7297a801e31282f6 (diff) | |
soc/intel/skylake: Use CPU MP Init Common code
This patch uses the common CPU Mp Init code.
BUG=none
BRANCH=none
TEST=Build and boot poppy
Change-Id: Ieb2f8ae25a31e86e9251fe97859678745fe610f5
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/cpu.h | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 6419bf8506..059367aaa9 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -23,17 +23,6 @@ /* CPU types */ #define SKYLAKE_FAMILY_ULT 0x406e0 -/* Supported CPUIDs */ -#define CPUID_SKYLAKE_C0 0x406e2 -#define CPUID_SKYLAKE_D0 0x406e3 -#define CPUID_SKYLAKE_HQ0 0x506e1 -#define CPUID_SKYLAKE_HR0 0x506e3 -#define CPUID_KABYLAKE_G0 0x406e8 -#define CPUID_KABYLAKE_H0 0x806e9 -#define CPUID_KABYLAKE_Y0 0x806ea -#define CPUID_KABYLAKE_HA0 0x506e8 -#define CPUID_KABYLAKE_HB0 0x906e9 - /* Latency times in units of 1024ns. */ #define C_STATE_LATENCY_CONTROL_0_LIMIT 0x4e #define C_STATE_LATENCY_CONTROL_1_LIMIT 0x76 @@ -67,7 +56,6 @@ void set_power_limits(u8 power_limit_1_time); u32 cpu_family_model(void); u32 cpu_stepping(void); int cpu_is_ult(void); -int is_secondary_thread(void); void configure_sgx(const void *microcode_patch); #endif |