diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2016-10-13 18:05:04 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-10-16 02:49:57 +0200 |
| commit | 29f8708fca820797a088c7e81eb830fc61b21d28 (patch) | |
| tree | 3270ceaf7ae8223cdf6f82776642e141e7436216 /src/soc/intel/skylake/include | |
| parent | c68ab5e8e5fbbd84c80e10ad70313a45fc8ca4db (diff) | |
soc/intel/skylake: Enable HECI BAR for ME communication
This patch programs and enables BAR for ME (bus:0/
device:0x16/function:0) device to have early ME communication.
BUG=none
BRANCH=none
TEST=Verified Global Reset MEI message can able to perform platform
global reset during romstage.
Change-Id: I99ce0ccd42610112a361a48ba31168c9feaa0332
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/17016
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/iomap.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index feba3027e7..e736d3b514 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -56,6 +56,8 @@ #define GPIO_BASE_SIZE 0x10000 +#define HECI1_BASE_ADDRESS 0xfed1a000 + /* * I/O port address space */ |