diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-07-24 17:10:31 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-07-29 19:31:07 +0200 |
| commit | 7f78849fc70879737260739034af4b2a99513e4d (patch) | |
| tree | b26830bf803930807c64f60f3479ec0a1cecca47 /src/soc/intel/skylake/include | |
| parent | 8dfa660a68be3e5268c78f2a6e6643795beed76f (diff) | |
skylake: align power management names with hardware
Some of the field and register names in the power management
code were not reflecting current chipset documentation. While
in there fix 0-sized array in the power_state structure. Lastly,
log the entire STD GPE register for visibility in elog. It reports
as an extension of other GPIO wake events.
BUG=None
BRANCH=None
TEST=Built and booted.
Change-Id: I57a621a418f90103ff92ddbf747e71a11d517c9a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ed15cc7d0aeee8070e134ed03e28fced9361c00e
Original-Change-Id: I19f9463c87e9472608e69d143932e66ea2b3c3e1
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/288296
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11070
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pm.h | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 6b75641178..0475e20d78 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -86,10 +86,12 @@ #define GPE0_STS(x) (0x80 + (x * 4)) #define GPE_31_0 0 /* 0x80/0x90 = GPE[31:0] */ #define GPE_63_32 1 /* 0x84/0x94 = GPE[63:32] */ -#define GPE_94_64 2 /* 0x88/0x98 = GPE[94:64] */ +#define GPE_95_64 2 /* 0x88/0x98 = GPE[95:64] */ #define GPE_STD 3 /* 0x8c/0x9c = Standard GPE */ #define WADT_STS (1 << 18) -#define GP27_STS (1 << 16) +#define LAN_WAK_STS (1 << 16) +#define GPIO_T2_STS (1 << 15) +#define ESPI_STS (1 << 14) #define PME_B0_STS (1 << 13) #define ME_SCI_STS (1 << 12) #define PME_STS (1 << 11) @@ -101,7 +103,9 @@ #define HOT_PLUG_STS (1 << 1) #define GPE0_EN(x) (0x90 + (x * 4)) #define WADT_EN (1 << 18) -#define GP27_EN (1 << 16) +#define LAN_WAK_EN (1 << 16) +#define GPIO_T2_EN (1 << 15) +#define ESPI_EN (1 << 14) #define PME_B0_EN (1 << 13) #define ME_SCI_EN (1 << 12) #define PME_EN (1 << 11) @@ -129,7 +133,7 @@ struct chipset_power_state { uint32_t gpe0_en[4]; uint32_t gen_pmcon_a; uint32_t gen_pmcon_b; - uint32_t gblrst_cause[0]; + uint32_t gblrst_cause[2]; uint32_t prev_sleep_state; } __attribute__ ((packed)); |