diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-07-17 16:52:10 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-07-21 21:20:12 +0200 |
| commit | 76d16715ec067abcadecbbd79b51e2711b8ec57c (patch) | |
| tree | 17d700d1df18492d40f8596bf8a0979ea7ac5a81 /src/soc/intel/skylake/include | |
| parent | d68c35dab4708566c760faa183eddf67bf5e2854 (diff) | |
skylake: add global reset cause registers to power state
Log the global reset causes in the power state structure.
While working in there pack the struct and use width-specific
types as this struct crosses the romstate <-> ramstage boundary.
Lastly, remove hsio version as it wasn't being written or read.
After global reset induced:
PM1_STS: 0000
PM1_EN: 0000
PM1_CNT: 00000000
TCO_STS: 0000 0000
GPE0_STS: 00000000 00000000 00000000 00000000
GPE0_EN: 00000000 00000000 00000000 00000000
GEN_PMCON: d8010200 00003808
GBLRST_CAUSE: 00000000 00040004
Previous Sleep State: S0
BUG=None
BRANCH=None
TEST=Induced global reset on glados using ETR3 register and write
to cf9.
Change-Id: I97b93de336e74c0e02199241376e74340612f0a7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bbc8f1d62131c0381e9d401f3281ee7a17fc2a47
Original-Change-Id: I1a8e5d07c6c0e09c163effe27491d8f198823617
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/286640
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11011
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pm.h | 7 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pmc.h | 2 |
2 files changed, 5 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 2e722bf206..6b75641178 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -129,10 +129,9 @@ struct chipset_power_state { uint32_t gpe0_en[4]; uint32_t gen_pmcon_a; uint32_t gen_pmcon_b; - int prev_sleep_state; - uint16_t hsio_version; - uint16_t hsio_checksum; -}; + uint32_t gblrst_cause[0]; + uint32_t prev_sleep_state; +} __attribute__ ((packed)); /* PM1_CNT */ void enable_pm1_control(uint32_t mask); diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h index 72c9a59e47..699e795dca 100644 --- a/src/soc/intel/skylake/include/soc/pmc.h +++ b/src/soc/intel/skylake/include/soc/pmc.h @@ -57,6 +57,8 @@ #define S5AC_GATE_SUS (1 << 14) #define PMSYNC_TPR_CFG 0xc4 #define PMSYNC_LOCK (1 << 31) +#define GBLRST_CAUSE0 0x124 +#define GBLRST_CAUSE1 0x128 /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ |