diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-07-22 20:57:05 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-07-29 19:30:13 +0200 |
| commit | 4f5efb6c21a9e909384a970bad410d11bdbda7a5 (patch) | |
| tree | 4596f402c78141eac1bdde0898541bcac5683137 /src/soc/intel/skylake/include | |
| parent | ed575681d1706783cc5cf75407490bc6d81a98d1 (diff) | |
skylake: prefix the gpio functions with 'gpio_'
In order to provide more clarity on what some of the gpio
functions are doing add a 'gpio_' prefix to the globally
visible functions.
BUG=chrome-os-partner:42982
BRANCH=None
TEST=Built glados.
Change-Id: I4cf48558c1eb9986ed52b160b6564ceaa3cb94b4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f79ef113797884063621fe6cd5cc374c53390ebd
Original-Change-Id: I0d8003efff77b92802e0caf8125046203f315ae4
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/288192
Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11067
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/gpio.h | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index 1d49a4599d..e8438ff99d 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -23,6 +23,23 @@ #include <stdint.h> +/* SOC has 8 GPIO communities GPP A~G, GPD */ +#define GPIO_COMMUNITY_MAX 8 + +typedef int gpio_t; + +/* Clear GPIO SMI Status */ +void gpio_clear_all_smi(void); + +/* Get GPIO SMI Status */ +void gpio_get_smi_status(u32 status[GPIO_COMMUNITY_MAX]); + +/* Enable GPIO SMI */ +void gpio_enable_all_smi(void); + +/* Enable GPIO individual Group SMI */ +void gpio_enable_groupsmi(gpio_t gpio_num, u32 mask); + /* * GPP_Ax to GPP_Gx; * where x=24 [between GPIO Community A to F] @@ -123,9 +140,6 @@ typedef struct { #define V_PCH_GPIO_GPP_G_PAD_MAX 8 #define V_PCH_GPIO_GPD_PAD_MAX 12 -/* SOC has 8 GPIO communities GPP A~G, GPD */ -#define GPIO_COMMUNITY_MAX 8 - #define GPIO_GET_GROUP_INDEX(group) (group & 0xFF) #define GPIO_GET_GROUP_INDEX_FROM_PAD(pad) (\ GPIO_GET_GROUP_INDEX((pad >> 16))) @@ -295,20 +309,6 @@ typedef enum { GpioResetResume = 0x7 /* Resume Reset */ } GPIO_RESET_CONFIG; -typedef int gpio_t; - -/* Clear GPIO SMI Status */ -void clear_all_smi(void); - -/* Get GPIO SMI Status */ -void get_smi_status(u32 status[GPIO_COMMUNITY_MAX]); - -/* Enable GPIO SMI */ -void enable_all_smi(void); - -/* Enable GPIO individual Group SMI */ -void enable_gpio_groupsmi(gpio_t gpio_num, u32 mask); - /* * GPIO Electrical Configuration * Set GPIO termination and Pad Tolerance (applicable only for some pads) |