diff options
| author | Barnali Sarkar <barnali.sarkar@intel.com> | 2016-08-02 17:49:56 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-08 18:18:57 +0200 |
| commit | 0dddcd76d74274715b0472ca41ddac88a5203b84 (patch) | |
| tree | e4c6370329abc5f2d3a283bf0b88cfab06c85a82 /src/soc/intel/skylake/include | |
| parent | 5d3d69ca950c728878d3fb0a26bc3be0b91bf406 (diff) | |
soc/intel/skylake: Cleanup patch for Skylake SoC
Here is the list of items of code cleanup
1. Define TCO registers in smbus.h and not in pmc.h (as per EDS).
2. Include smbus.h wherever these TCO register defines were used.
3. Remove duplication of define in gpio_defs.h.
4. Remove unnecessary console.h include from memmap.h as no prints done.
5. Remove unnecessary comment from pch.c.
BUG=none
BRANCH=none
TEST=Built and boot kunimitsu.
Change-Id: Ibe6d2537ddde3c1c7f8ea5ada1bfaa9be79c0e3b
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16027
Tested-by: build bot (Jenkins)
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/gpio_defs.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pmc.h | 10 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/smbus.h | 9 |
3 files changed, 9 insertions, 11 deletions
diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 4008dfe31d..112db63e18 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -482,7 +482,6 @@ /* GPIOTXSTATE - Drive value onto pad */ #define GPIOTXSTATE_SHIFT 0 #define GPIOTXSTATE_MASK 0x1 -#define PAD_CFG_DW_OFFSET 0x400 /* TERM - termination control */ #define PAD_TERM_SHIFT 10 #define PAD_TERM_MASK 0xf diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h index 9c9b175285..10ea6ae894 100644 --- a/src/soc/intel/skylake/include/soc/pmc.h +++ b/src/soc/intel/skylake/include/soc/pmc.h @@ -99,14 +99,4 @@ #define GBLRST_CAUSE0 0x124 #define GBLRST_CAUSE1 0x128 - -/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ -#define TCO1_STS 0x04 -#define TCO2_STS 0x06 -#define TCO2_STS_SECOND_TO 0x02 -#define TCO2_STS_BOOT 0x04 -#define TCO1_CNT 0x08 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HLT (1 << 11) - #endif diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h index c395c8ed19..ff89f3ab28 100644 --- a/src/soc/intel/skylake/include/soc/smbus.h +++ b/src/soc/intel/skylake/include/soc/smbus.h @@ -27,6 +27,15 @@ /* SMBUS TCO base address. */ #define TCOBASE 0x50 +/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ +#define TCO1_STS 0x04 +#define TCO2_STS 0x06 +#define TCO2_STS_SECOND_TO 0x02 +#define TCO2_STS_BOOT 0x04 +#define TCO1_CNT 0x08 +#define TCO_LOCK (1 << 12) +#define TCO_TMR_HLT (1 << 11) + /* SMBus I/O bits. */ #define SMBHSTSTAT 0x0 #define SMBHSTCTL 0x2 |