skylake: Add initial FSP2.0 support

Add Initial pieces of code to support fsp2.0 in skylake keeping
the fsp1.1 flow intact.

The soc/romstage.h and soc/ramstage.h have a reference to
fsp driver includes, so split these header files for
each version of FSP driver.

Add the below files,
car_stage.S:
	Add romstage entry point (car_stage_entry).
	This calls into romstage_fsp20.c and aslo handles
	the car teardown.
romstage_fsp20.c:
	Call fsp_memory_init() and also has the callback
	for filling memory init parameters.

Also add monotonic_timer.c to verstage.

With this patchset and relevant change in kunimitsu mainboard,
we are able to boot to romstage.

TEST= Build and Boot Kunimitsu with PLATFORM_USES_FSP1_1
Build and Boot Kunimitsu to romstage with PLATFORM_USES_FSP2_0

Change-Id: I4309c8d4369c84d2bd1b13e8ab7bfeaaec645520
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16267
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

6 files changed, 81 insertions, 5 deletions

diff --git a/src/soc/intel/skylake/include/soc/ramstage.h b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
index 55f9972e4a..e469554ba2 100644
--- a/src/soc/intel/skylake/include/soc/ramstage.h
+++ b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
@@ -19,13 +19,18 @@
 
 #include <chip.h>
 #include <device/device.h>
+#include <fsp/gop.h>
 #include <fsp/ramstage.h>
+#include <fsp/soc_binding.h>
+
+#define FSP_SIL_UPD SILICON_INIT_UPD
+#define FSP_MEM_UPD MEMORY_INIT_UPD
 
 void pch_enable_dev(device_t dev);
 void soc_init_pre_device(void *chip_info);
 void soc_init_cpus(device_t dev);
 const char *soc_acpi_name(struct device *dev);
-
+int init_igd_opregion(igd_opregion_t *igd_opregion);
 extern struct pci_operations soc_pci_ops;
 
 #endif
diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/fsp11/soc/romstage.h
index 6c40bd626d..6c40bd626d 100644
--- a/src/soc/intel/skylake/include/soc/romstage.h
+++ b/src/soc/intel/skylake/include/fsp11/soc/romstage.h
diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
new file mode 100644
index 0000000000..3a9d96bbdd
--- /dev/null
+++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_RAMSTAGE_H_
+#define _SOC_RAMSTAGE_H_
+
+#include <chip.h>
+#include <device/device.h>
+
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <soc/intel/common/opregion.h>
+
+#define FSP_SIL_UPD struct FSP_S_CONFIG
+#define FSP_MEM_UPD struct FSP_M_CONFIG
+
+void intel_silicon_init(void);
+void mainboard_silicon_init_params(struct FSP_S_CONFIG *params);
+void pch_enable_dev(device_t dev);
+void soc_init_pre_device(void *chip_info);
+void soc_init_cpus(device_t dev);
+const char *soc_acpi_name(struct device *dev);
+
+extern struct pci_operations soc_pci_ops;
+
+#endif
diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h
new file mode 100644
index 0000000000..d48ac67ab3
--- /dev/null
+++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_ROMSTAGE_H_
+#define _SOC_ROMSTAGE_H_
+
+#include <arch/cpu.h>
+#include <fsp/api.h>
+
+asmlinkage void *car_stage_c_entry(void);
+void mainboard_memory_init_params(struct FSPM_UPD *mupd);
+
+void systemagent_early_init(void);
+int smbus_read_byte(unsigned device, unsigned address);
+int early_spi_read_wpsr(u8 *sr);
+
+#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h
index fa8da46f5a..1beaaa4986 100644
--- a/src/soc/intel/skylake/include/soc/smm.h
+++ b/src/soc/intel/skylake/include/soc/smm.h
@@ -20,7 +20,6 @@
 #include <stdint.h>
 #include <cpu/x86/msr.h>
 #include <fsp/memmap.h>
-#include <fsp/romstage.h>
 #include <soc/gpio.h>
 
 struct ied_header {
diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h
index d70fd21304..1c19b8870e 100644
--- a/src/soc/intel/skylake/include/soc/vr_config.h
+++ b/src/soc/intel/skylake/include/soc/vr_config.h
@@ -19,7 +19,11 @@
 #ifndef _SOC_VR_CONFIG_H_
 #define _SOC_VR_CONFIG_H_
 
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
 #include <fsp/soc_binding.h>
+#else
+#include <fsp/api.h>
+#endif
 
 struct vr_config {
 
@@ -74,7 +78,6 @@ enum vr_domain{
 	NUM_VR_DOMAINS
 };
 
-void fill_vr_domain_config(SILICON_INIT_UPD *params, int domain,
-				const struct vr_config *cfg);
-
+void fill_vr_domain_config(void *params,
+			int domain, const struct vr_config *cfg);
 #endif