diff options
| author | Barnali Sarkar <barnali.sarkar@intel.com> | 2017-03-31 18:11:49 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-05-02 18:26:07 +0200 |
| commit | 7146445be9618eb47895782912af28fb627c009d (patch) | |
| tree | ec95cd0ab17fecd4ce91bb9b6bff459d9459f3f4 /src/soc/intel/skylake/include/fsp20 | |
| parent | c261c4b426ac806cca732bb30459f0e6e855828a (diff) | |
soc/intel/skylake: Clean up code by using common FAST_SPI module
This patch currently contains the following -
1. Use SOC_INTEL_COMMON_BLOCK_FAST_SPI kconfig for common FAST_SPI code.
2. Perform FAST_SPI programming by calling APIs from common FAST_SPI library.
3. Use common FAST_SPI header file.
Change-Id: I4fc90504d322db70ed4ea644b1593cc0605b5fe8
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/19055
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake/include/fsp20')
| -rw-r--r-- | src/soc/intel/skylake/include/fsp20/soc/romstage.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h index 6bdc3b5858..cdcc8fbc28 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/romstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h @@ -23,7 +23,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); int smbus_read_byte(unsigned int device, unsigned int address); -int early_spi_read_wpsr(u8 *sr); /* Board type */ enum board_type { BOARD_TYPE_MOBILE = 0, |