skylake: Add initial FSP2.0 support

Add Initial pieces of code to support fsp2.0 in skylake keeping
the fsp1.1 flow intact.

The soc/romstage.h and soc/ramstage.h have a reference to
fsp driver includes, so split these header files for
each version of FSP driver.

Add the below files,
car_stage.S:
	Add romstage entry point (car_stage_entry).
	This calls into romstage_fsp20.c and aslo handles
	the car teardown.
romstage_fsp20.c:
	Call fsp_memory_init() and also has the callback
	for filling memory init parameters.

Also add monotonic_timer.c to verstage.

With this patchset and relevant change in kunimitsu mainboard,
we are able to boot to romstage.

TEST= Build and Boot Kunimitsu with PLATFORM_USES_FSP1_1
Build and Boot Kunimitsu to romstage with PLATFORM_USES_FSP2_0

Change-Id: I4309c8d4369c84d2bd1b13e8ab7bfeaaec645520
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16267
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

2 files changed, 66 insertions, 0 deletions

diff --git a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
new file mode 100644
index 0000000000..e469554ba2
--- /dev/null
+++ b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_RAMSTAGE_H_
+#define _SOC_RAMSTAGE_H_
+
+#include <chip.h>
+#include <device/device.h>
+#include <fsp/gop.h>
+#include <fsp/ramstage.h>
+#include <fsp/soc_binding.h>
+
+#define FSP_SIL_UPD SILICON_INIT_UPD
+#define FSP_MEM_UPD MEMORY_INIT_UPD
+
+void pch_enable_dev(device_t dev);
+void soc_init_pre_device(void *chip_info);
+void soc_init_cpus(device_t dev);
+const char *soc_acpi_name(struct device *dev);
+int init_igd_opregion(igd_opregion_t *igd_opregion);
+extern struct pci_operations soc_pci_ops;
+
+#endif
diff --git a/src/soc/intel/skylake/include/fsp11/soc/romstage.h b/src/soc/intel/skylake/include/fsp11/soc/romstage.h
new file mode 100644
index 0000000000..6c40bd626d
--- /dev/null
+++ b/src/soc/intel/skylake/include/fsp11/soc/romstage.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_ROMSTAGE_H_
+#define _SOC_ROMSTAGE_H_
+
+#include <fsp/romstage.h>
+
+void systemagent_early_init(void);
+void intel_early_me_status(void);
+void enable_smbus(void);
+int smbus_read_byte(unsigned device, unsigned address);
+
+int early_spi_read_wpsr(u8 *sr);
+void mainboard_fill_spd_data(struct pei_data *pei_data);
+
+#endif /* _SOC_ROMSTAGE_H_ */