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| author | Wisley Chen <wisley.chen@quantatw.com> | 2017-02-10 04:43:29 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-02-13 18:24:40 +0100 |
| commit | b3b453f93c675786479270ac8234d4cdad86ddf5 (patch) | |
| tree | 86809b9f29711fa0e71a79bf4f830f49cf1556a1 /src/soc/intel/skylake/i2c.c | |
| parent | 85cfddb4b493004d7fe2073a9db96cade40c91f8 (diff) | |
mainboard/google/snappy: Update DPTF settings
Update DPTF parameters based on thermal team test result.
1. Update TSR2 trigger points.
TSR2 passive point: 70, critical point: 90
2. Set PL2 Max to 15W.
BUG=chrome-os-partner:61383
BRANCH=reef
TEST=build, boot on snappy, and verified by thermal team
Change-Id: I8d01d6c1d7eabd359ceb131f3cd10965d4ac2c42
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18318
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/i2c.c')
0 files changed, 0 insertions, 0 deletions