summaryrefslogtreecommitdiff
path: root/src/soc/intel/skylake/gspi.c
diff options
context:
space:
mode:
authorren kuo <ren.kuo@quantatw.com>2017-11-03 18:00:11 +0800
committerPatrick Georgi <pgeorgi@google.com>2017-11-06 13:55:46 +0000
commit6d53c6bc6a248439de78d498a13441a6925ab713 (patch)
tree8d6f787e239326c1b27923fb541bddd9073f2a65 /src/soc/intel/skylake/gspi.c
parent64f87f35412b24509123860b7cf6bdc9e6fab9f9 (diff)
mainboard/google/coral: Override VBT selection for astronaut
Current VBT setting for T8 is only 1ms which is under Innolux N116BCA-EA1 panel's spec. Modify T8 to 100ms. (Innolux's panel's spec requires T8 needs to be greater than 80ms) CQ-DEPEND=CL:*496012 BUG=b:67756548 BRANCH=master TEST=emerge-coral depthcharge coreboot chromeos-bootimage Run on DUT and check panel sequence meets spec. Change-Id: I580567decfccd78366c37181255015ac2cd76493 Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Reviewed-on: https://review.coreboot.org/22306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quantatw.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/skylake/gspi.c')
0 files changed, 0 insertions, 0 deletions