diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2016-11-23 00:54:47 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-30 16:54:36 +0100 |
| commit | 0068dfdcc8c2a80508cdd44909d9a2561a30a0e5 (patch) | |
| tree | 5ddb85a539c8d65c3535879b19dc7133c054a4ff /src/soc/intel/skylake/gpio.c | |
| parent | eedf6d8aa81e85b52d3c150dc992cbfb3077988d (diff) | |
soc/intel/skylake: Remove pad configuration size hardcoding
Existing GPIO driver inside coreboot use some hardcoded magic number
to calculate gpio pad offset. Avoid this kind of hardcoding.
Change-Id: I6110435574b141c57f366ccb1fbe9bf49d4dd70a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/17571
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/gpio.c')
| -rw-r--r-- | src/soc/intel/skylake/gpio.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 5b9babfde3..6334b3e9bd 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -226,7 +226,8 @@ static void *gpio_dw_regs(gpio_t pad) pad_relative = pad - comm->min; /* DW0 and DW1 regs are 4 bytes each. */ - return ®s[PAD_CFG_DW_OFFSET + pad_relative * 8]; + return ®s[PAD_CFG_DW_OFFSET + pad_relative * + GPIO_DWx_SIZE(GPIO_DWx_COUNT)]; } static void *gpio_hostsw_reg(gpio_t pad, size_t *bit) |